Exemplary embodiments relate generally to a nonvolatile memory device.
An erase operation for erasing data stored in a memory cell of a semiconductor memory device (in particular, a nonvolatile semiconductor memory device) which can be electrically erased and programmed and a program operation for programming data into a memory cell of the semiconductor memory device are performed through Fowler-Nordheim (F-N) tunneling and a hot electron injection method.
A NAND flash memory device (i.e., a nonvolatile memory device) includes page buffers, each reading data stored in a memory cell and storing the read data. An input and output (hereinafter referred to as ‘I/O’) line for outputting data output by the page buffer has an I/O pair structure.
FIG. 1A is a diagram showing a nonvolatile memory device 100.
Referring to FIG. 1A, the nonvolatile memory device 100 includes a memory cell array 110, a page buffer unit 120, a Y decoder unit 130, and an I/O control unit 140.
The memory cell array 110 includes a plurality of memory cells (not shown). The memory cells are coupled to bit lines BL[0] to BL[M+7].
The page buffer unit 120 includes page buffers PB[0] to PB[M+7] each coupled to one or more bit lines. In the nonvolatile memory device 100 of FIG. 1A, one page buffer is illustrated to be coupled to one bit line BL.
Each of the page buffers PB[0] to PB[M+7] receives data to be programmed into a selected one of the memory cells, coupled to the bit line BL coupled thereto, or reads data stored in a selected memory cell and stores and outputs the read data.
The Y decoder unit 130 couples the I/O control unit 140 and a selected one of the page buffers PB[0] to PB[M+7] together in response to a control signal.
The I/O control unit 140 performs the I/O of data between a page buffer, selected by the Y decoder unit 130, and an external I/O pad (not shown) of the nonvolatile memory device 100. The I/O control unit 140 includes a first I/O controller IO_CTL[0] to an eighth I/O controller IO_CTL[7].
As shown in FIG. 1A, the I/O control unit 140 of the nonvolatile memory device 100 includes the eight I/O controllers IO_CTL[0] and IO_CTL[7]. Accordingly, to comply with the layout of the eight I/O controllers IO_CTL, the page buffers PB[0] to PB[M+7] of the page buffer unit 120 have an eight-stage structure.
The page buffer unit 120 is configured in such a manner that the eight page buffers PB[0] to PB[7] forms a column, the page buffers PB[8] to PB[15] form a next column, and so on. The page buffer rows are configured in a row direction. In FIG. 1A, the number of page buffer columns is (N), and the number of page buffer rows is eight. Accordingly, M may be a multiple of the number of page buffers comprising a column of the page buffer unit 120. PB[M] may correspond to a page buffer in the first row and the last or right most column of the page buffers comprising the page buffer unit 120. Thus, for example, if the page buffer unit 120 comprises eight rows and eight columns, page buffer PB[M] may correspond to page buffer PB[56], and page buffer PB[M+1] may correspond to page buffer PB[57], etc. The variable M may also correspond to various bit lines. Thus, the first bit line may correspond to BL[M] when M is 0, etc.
The Y decoder unit 130 includes a 0th decoder PB_DEC[0] to an Nth decoder PB_DEC[N] for selecting the page buffers in the respective page buffer stages. The page buffer unit 120 may comprise N columns, and an Nth column may refer to a particular column included in the page buffer unit 120. The variable N may be used as a zero based identifier of various components. For example, when N is ‘0’ N may correspond to the first page buffer decoder PB_DEC[0]. Each of the decoders PB_DEC is coupled to each of the page buffer columns, each including the eight page buffers, and is configured to output a control signal to select the eight page buffers.
Each of the page buffer rows is coupled to a respective pair of I/O lines, such as I/O line pair IO[0] and IOB[0] to I/O line pair IO[7] and IOB[7]. The pairs of I/O lines are respectively coupled to the first I/O controller IO_CTL[0] through the eighth I/O controller IO_CTL[7].
For example, the pair of I/O lines IO[0] and IOB[0] are respectively coupled to the first I/O controller IO_CTL[0], while the pair of I/O lines IO[7] and IOB[7] are respectively coupled to the to the eighth I/O controller IO_CTL[7].
FIG. 1B is a circuit diagram of part of the page buffer unit 120 shown in FIG. 1A. This figure shows a simplified diagram of one of the page buffer rows of the page buffer unit 120 shown in FIG. 1A. Only the latches L of the page buffers are shown in order to illustrate a connection relationship between the page buffers and the I/O lines.
Of the page buffers, the page buffer PB[0] . . . PB[M] are shown and PB[0] is described as an example with reference to FIG. 1B. The remaining page buffers have the same construction as the page buffer PB[0].
The page buffer PB[0] includes a first latch L0 and first to fifth NMOS transistors N1 to N5.
The first latch L0 is configured to include two inverters and coupled between a node K1 and a node K2. The first and fourth NMOS transistors N1, N4 are in series coupled between the node K1 and a node K4. The second and fifth NMOS transistors N2, N5 are coupled in series between the node K2 and a node K5.
The third NMOS transistor N3 is coupled between the sense node SO of the page buffer and the node K3 of the second and fifth NMOS transistors N2, N5.
A first selection enable signal CENB is inputted to the gates of the first and second NMOS transistors N1, N2. A first selection signal CS[0] is inputted to the gates of the fourth and fifth NMOS transistors N4, N5. A second selection enable signal CEN is inputted to the gate of the third NMOS transistor N3.
The first I/O lines IO[0] and IOB[0] are respectively coupled to the node K4 and the node K5. The operation of the page buffer PB[0] is described later.
FIG. 1C is a circuit diagram of the Y decoder unit 130 shown in FIG. 1A.
Referring to FIG. 1C, the Y decoder unit 130 includes the first decoder PB_DEC[0] to the Nth decoder PB_DEC[N]. Since each of the N decoders, PB_DEC[0] through PB_DEC[N], have the same construction, only the first decoder PB_DEC[0] is described as an example.
The first decoder PB_DEC[0] includes a first PMOS transistor P1, a first inverter IN1, and sixth to ninth NMOS transistors N6 to N9.
The first PMOS transistor P1 is coupled between a power supply voltage and a node K6. The gate of the first PMOS transistor P1 is coupled to a ground node. Accordingly, the first PMOS transistor P1 maintains a turn-on state.
The sixth to ninth NMOS transistors N6 to N9 are coupled in series between the node K6 and the ground node. A page buffer selection signal PBSEL is inputted to the gate of the sixth NMOS transistor N6. Y address signals YP[0], YA[0], and YB[0] are respectively inputted to the gates of the seventh to ninth NMOS transistors N7 to N9.
The Y address signals YP[0], YA[0], and YB[0] are used to select the page buffer stage. The Y address signals YP[0], YA[0], and YB[0] may be inputted to the decoders PB_DEC in different combinations as needed for the purpose of selecting the appropriate page buffer stage.
The first inverter IN1 inverts a voltage level of the node K6 and outputs the inverted voltage level as the selection signal CS[0].
The first I/O controller IO_CTL[0] which is coupled to the pair of I/O lines IO[0], IOB[0], has a construction such as that shown in FIG. 1D.
That is, FIG. 1D is a circuit diagram of the first controller IO_CTL[0] of the I/O control unit 140 shown in FIG. 1A.
Referring to FIG. 1D, the first I/O controller IO_CTL[0] includes a tenth NMOS transistor N10, a second inverter IN2, and an I/O sense amp (IOSA) 141.
The IOSA 141 senses data received from the pair of I/O lines IO[0], IOB[0] and amplifies and outputs the sensed data.
The tenth NMOS transistor N10 is coupled between the I/O line IOB[0] and a node K7. The second selection enable signal CEN is inputted to the gate of the tenth NMOS transistor N10.
The second inverter IN2 inverts data output from the IOSA 141 and outputs the inverted data to the node K7. The node K7 is coupled to a first data line DL[0].
The second inverter IN2 is operated in response to first and second data output enable signals DOEN and DOENB.
In the page buffer PB[0], and with the nonvolatile memory device 100 configured as described above with reference to FIGS. 1B to 1D, the control signal is inputted as follows in order to output data.
To output data stored in the first latch L[0], the first selection enable signal CENB is maintained at a high level, and the second selection enable signal CEN is maintained at a low level. “High level” and “low level” refers to, for example, the reference voltage levels applied or maintained at the various nodes as inputs or outputs. It is to be understood that, a high level or low level may correspond to voltage ranges that are predetermined to represent the high level or low level and not necessarily to any specific values. It is also to be understood that “high level” and “low level” may also be referred to as “logic levels” for example, a “high logic level” and a “low logic level,” respectively.
The first and second NMOS transistors N1, N2 are turned on in response to the first selection enable signal CENB of a high level. Since the second selection enable signal CEN is maintained at a low level, the third NMOS transistor N3 is turned off.
To output data stored in the page buffer column including the page buffer PB[0], the first decoder PB_DEC[0] outputs the first selection signal CS[0] at a high level.
To this end, the page buffer selection signal PBSEL and the Y address signals YP[0], YA[0], and YB[0] are also at a high level and are inputted to the first decoder PB_DEC[0]. In response thereto, when the sixth to ninth NMOS transistors N6 to N9 are turned on, the node K6 is coupled to the ground node. Accordingly, the first selection signal CS[0] is at a high level, because the ground node at K6 becomes the input to the first inverter IN1 and is therefore inverted by the first inverter IN1, and output as CS[0] at a high level.
The fourth and fifth NMOS transistors N4, N5 of the page buffer PB[0] are turned on in response to the first selection signal CS[0] being at a high level as described above. Accordingly, data stored in the node K1 and data stored in the node K2, of the first latch L0, are respectively output to the I/O lines IO[0], IOB[0].
The IOSA 141 of the first I/O controller IO_CTL[0], which is coupled to the I/O lines IO[0], IOB[0], senses the data received from the I/O lines IO[0], IOB[0] and outputs the sensed data.
To output the data, the second inverter IN2 is operated in response to the first data output enable signal DOEN being at a high level and the second data output enable signal DOENB being at a low level. Accordingly, the data output from the IOSA 141 is inverted by the second inverter IN2 and then output to the first data line DL[0] via the node K7.
In the data output operation, in the state in which the first selection signal CS[0] of a high level has been received, data stored in the eight page buffers PB[0] to PB[7], each page buffer belonging to one page buffer stage, are respectively output through the first to eighth I/O controllers IO_CTL[0] to IO-CTL[7].
During the time for which data are not output, the first selection enable signal CENB shifts to a low level, and the second selection enable signal CEN shifts to a high level.
If the second selection enable signal CEN of a high level is received, the third NMOS transistor N3 is coupled to the sense node SO of the page buffer PB and is operated in a cell current measurement mode (CELL IV mode) in which current is measured in order to check a state of the threshold voltages of the memory cells of the memory cell array 110 which have been programmed. In the cell current measurement mode, the first selection enable signal CENB is maintained at a low level and the second selection enable signal CEN is maintained at a high level. The first selection signal CS[0] of a high level is inputted to the fourth and fifth NMOS transistors N4, N5.
The sense node SO of the page buffer PB[0] is coupled to a memory cell selected in order to measure its cell current, and so the cell current flows through the memory cell. When the third and fifth NMOS transistors N3, N5 are turned on, the cell current is transferred to the I/O line IOB[0].
In the first I/O controller IO_CTL[0], the tenth NMOS transistor N10 is turned on in response to the second selection enable signal CEN of a high level. Accordingly, the cell current is output to the first data line DL[0] via the I/O line IOB[0].
As described above, the page buffer PB[0] includes the first and second NMOS transistors N1, N2 turned on when data are inputted and output and the third NMOS transistor N3 configured to measure a cell current.
In this case, when data stored in the page buffer PB[0] are output, the first NMOS transistor N1 and the fourth NMOS transistor N4 are coupled in series together, and the second NMOS transistor N2 and the fifth NMOS transistor N5 are coupled in series together. However, the structure in which the MOS transistors are coupled in series together becomes a factor to deteriorate the performance of data input and output.
As described above, the page buffer requires two NMOS transistors for inputting and outputting data and one NMOS transistor for measuring a cell current. Accordingly, the number of elements is increased, thereby requiring eight stages. Consequently, the layout area constituting the page buffer is increased.